Presently, there is a great demand for shrinking semiconductor devices to provide an increased density of devices on the semiconductor chip that are faster and consume less power. The scaling of the devices in the lateral dimension requires vertical scaling as well so as to achieve adequate device performance. This vertical scaling requires the thickness of the gate dielectric to be reduced so as to provide the required device performance. However, thinning of the gate dielectric provides a smaller barrier to dopant diffusion from a polysilicon gate structure or metal diffusion from a metal gate structure and through the underlying dielectric and it may result in devices with diminished electrical performance and reliability.
In addition, with this decrease in the physical thickness of the gate dielectric, device reliability will be degraded due to the requirements for increased direct tunneling current through the gate dielectric. In order to increase the effects of direct tunneling, a gate dielectric with a dielectric constant greater than that of the standard gate dielectric, thermally grown silicon dioxide, can be used. This will facilitate an increased gate dielectric thickness for a given gate dielectric area.
One means of reducing these problems is to use silicon nitride as the gate dielectric layer. Silicon nitride has a higher dielectric constant than typical thermally grown SiO2 films and it provides greater resistance to impurity diffusion. However, the electrical properties of standard deposited silicon nitride films are far inferior to thermal oxides. Hence, to make the conventional silicon nitride film useful as a gate insulator, an oxide layer must be formed between the nitride layer and the substrate.
Recently, a technique was developed for depositing a silicon nitride film that has electrical properties similar to that of typical silicon oxide films. This new technique is referred to as Jet Vapor Deposition (JVD). See Xie-wen Wang, et al., Highly reliable Silicon Nitride Thin Films Made by Jet Vapor Deposition, JPN. J. APPL. PHYS., Vol. 34, 955–958 (1995). JVD relies on a supersonic jet of a light carrier gas, such as helium, to transport deposition vapor from the source to the substrate. While this technique yields a silicon nitride film that can be used as a gate dielectric, it suffers from the following problems: it is a relatively complex process which involves rastering the plasma jet across the wafer so as to deposit the film on the entire wafer (and this is difficult to reliably accomplish); this process can not be easily scaled up for broad-area film formation on large diameter wafers (e.g. 8–12 inch wafers); hydrogen is incorporated into the resultant film; and this process is a low throughput process because of the tremendously slow deposition rates. In addition, most CVD-type techniques yield a high density of surface electrical interface states, high leakage, and instabilities. All of these problems have adverse affects to device performance.
Another method of maintaining the benefit of the electrical properties of the oxide film while also getting the barrier properties of a nitride film is accomplished by incorporating nitrogen into a gate oxide layer. Typically, this is accomplished by a reoxidized nitrided oxide process. This process involves using ammonia to include nitrogen within the gate oxide layer. Unfortunately, in order to get the ammonia to penetrate the gate oxide, temperatures in excess of 1000 C are required. In addition, once the high temperature reaction has begun, it is difficult to control the concentration of the nitrogen incorporated into the gate oxide. Excessive nitrogen near the interface between the semiconductor substrate and the gate oxide can adversely affect the threshold voltage and degrade the channel mobility of the device through Coloumbic effects of the fixed charge and interface-trap charge associated with the nitrogen on the carriers within the channel region.
Other experimental work has been done involving nitridation through exposure to a remote plasma. See S. V. Hattangady, et al., Controlled Nitrogen Incorporation at the Gate Oxide Surface, 66 Appl. Phys. Lett. 3495 Jun. 19, 1995). This process provided for nitrogen incorporation specifically at the gate-conductor interface using a high pressure (100 milliTorr) and low power (30 Watt) process with relatively low ion-density and ion flux. Low ion-density and ion-flux dictates a long duration (around 10–60 minute) so as to obtain desired concentration of incorporated nitrogen. This long exposure to the plasma increases the probability of charge-induced damage to the oxide.